1. Field of the Invention
The present invention relates to a logarithm computing circuit, and particularly to a logarithm computing circuit that computes a logarithm to base 2 of a number of a fixed point representation.
2. Description of the Related Art
In a logarithm computing circuit that performs base-2-logarithmic conversion (conversion to a logarithm to base 2), an inputted value N (N&gt;0) is divided into an exponent part Ne and a mantissa part Nm. EQU N=N.sub.m .multidot.2.sup.N e (N.sub.e is an integer, and -1&lt;N.sub.m &lt;1)(1)
Logarithmic calculation for this N has conventionally been performed as follows: ##EQU1##
In other words, the logarithmic conversion of N can be carried out by performing the base-2-logarithmic conversion of the mantissa part N.sub.m and adding the logarithmic-converted value and the exponent part N.sub.e. All discussion hereinafter will assume that 2 is taken as the base.
In cases in which an inputted N is represented by a fixed point system, the calculation of formula (2) is carried out as follows: Assuming the most significant bit is a sign bit, the numeral of each bit of inputted N is first shifted in the direction of the most significant bit with the radix point fixed as is until the bit following the most significant bit becomes 1. Here, the number of bits the inputted N is shifted is noted as a shift number p. Next, the radix point is shifted to a position between the most significant bit and the next bit (hereinafter referred to as the normal position). Here, the bit number of the shift made by the radix point is noted as a correction number q. Through these operations, the inputted N is converted to a form wherein the radix point is at the normal position and the bit following the most significant bit is 1. This form will hereinafter be noted as the normal form of inputted N, and the process by which inputted N is converted to the normal form will be noted as normalization. The shift of shift number p is equivalent to multiplying the input N by 2.sup.p, and the radix point shift of correction number q is equivalent to multiplying the input N by 2.sup.-q. Consequently, normalization of input N corresponds to multiplying the input N by 2.sup.P-q. When input N is represented in the form of formula (1), mantissa part N.sub.m is the normalized form of input N, and N.sub.e of formula (1) becomes equal to q-p. For this reason, the calculation of formula (2) is realized by making q-p the exponent part N.sub.e, making the normal form of input N the mantissa part N.sub.m and finding the logarithm log.sub.2 N.sub.m, and calculating the sum of the two.
Consequently, when the fixed point of input N is at the normal position (q=0), -p is equal to the value of the exponent part N.sub.e. When the fixed point of input N is displaced from the normal position by just q digits, the exponent part N.sub.e becomes the integer -(p-q) obtained by correcting the shift number p by the correction number q. For example, in a case in which the fixed point of input N lies between the eighth and ninth bit from the most significant bit, the correction number is 7, and the value obtained by subtracting the shift number from this correction number is equal to the exponent part.
When the input value is, for another example, 1.5 (00000001.100 . . . in binary number representation), 6 shifts in the direction of the most significant bit are necessary before the bit following the most significant bit becomes 1, and for this reason, the shift number is 6, and the input value is converted to 01100000.000 . . . in binary representation by the six-bit shift. Next, the position of the radix point is shifted seven times in order to effect the normalization, whereby the mantissa value becomes 0.75 (0.110000 . . . in binary representation). Consequently, the logarithmic conversion of 1.5 as defined to base 2 can be obtained according to the following formula: ##EQU2##
FIG. 1 is a block diagram showing a conventional circuit that realizes the base-2 logarithm computing circuit in accordance with the above method. FIG. 2 is a block diagram showing the shift number detection circuit 7 of FIG. 1.
The logarithm computing circuit is composed of a shift number detector 7, a shifter 2, a base-2-logarithmic converter 8, and an adder 9, and as shown in FIG. 2, the shift number detector 7 is made up of a bit position detector 4, a shift number converter 5, and an exponent part converter 10.
In FIG. 1, input 101 is a number in fixed point representation supplied for the purpose of performing logarithm computation. The shift number detector 7 establishes a shift number 102 for the purpose of performing normalization of the input 101, and also performs correction of the shift number with the radix point position, thereby providing an exponent value 106. Here, the bit position detector 4 detects the first bit position of binary 1 as viewed from the side of the most significant bit of the input 101. The exponent part converter 10 outputs the exponent value 106. The shift number converter 5 outputs the shift number 102.
In FIG. 1, the shifter 2 receives the input 101 and the shift number 102 delivered from the shift number detector 7, and in accordance with the shift number, carries out normalization of the input 101 and outputs the mantissa part 103. The range of the value of this mantissa part can be expressed as follows: EQU 0.5.ltoreq.mantissa value&lt;1 (4)
This mantissa part 103 is converted to its base-2 logarithm by means of the logarithmic converter 8. As a result, the range of the output 107 of the logarithmic converter 8 is given by the following formula: EQU -1.ltoreq.logarithmic converter output&lt;0 (5)
This logarithmic converter output 107 is added to the exponent part 106 supplied from the shift number detector 7 by the adder 9, which provides logarithmic conversion output 108. In this addition process, because the exponent part 106 is an integer value, a carry operation resulting from the addition occurs only when the output 107 of the logarithmic converter 8 is -1. Accordingly, the adder 9 is necessary only for addition of logarithmic converter output that is equal to -1, and is essentially unnecessary for any other purposes, because, when the output 107 of the logarithmic converter 8 is not equal to -1, the numerical representation of the sum of the exponent part 106 and the logarithmic converter output 107 is obtained without any substantial addition calculation by simply arranging the output 107 in line with the exponent part 106. Nevertheless, conventional logarithm computing circuits are provided with adders for carrying out only the addition of -1, giving rise to the problem of poor efficiency of the circuit structure.